1. Field of the Invention
The invention relates to a method for fabricating MOS transistors, and more particularly, to a method of using epitaxial selective growth process for fabricating MOS transistors.
2. Description of the Prior Art
A conventional MOS transistor generally includes a semiconductor substrate, such as silicon, a source region, a drain region, a channel positioned between the source region and the drain region, and a gate located above the channel. The gate is composed of a gate dielectric layer, a gate conductive layer positioned on the gate dielectric layer, and a plurality of spacers positioned on the sidewalls of the gate conductive layer. Generally, for a given electric field across the channel of a MOS transistor, the amount of current that flows through the channel is directly proportional to a mobility of the carriers in the channel. Therefore, how to improve the carrier mobility so as to increase the speed performance of MOS transistors has become a major topic for study in the semiconductor field.
The formation of SiGe source/drain regions is commonly achieved by epitaxially growing a SiGe layer adjacent to the spacers within the semiconductor substrate after forming the spacer. In this type of MOS transistor, a biaxial tensile strain occurs in the epitaxial silicon layer due to the silicon germanium, which has a larger lattice constant than silicon, and, as a result, the band structure alters, and the carrier mobility increases. This enhances the speed performance of the MOS transistor.
However, it should be noted in the conventional art for conducting selective epitaxial growth process to form epitaxial layer, the epitaxial layer is typically grown against the sidewall of the spacer. This type of growing behavior often causes reduced strain in the channel region of the transistor and induces a Ion degradation phenomenon. As a result, the performance of the device is greatly affected.